1. Field of the Invention
This invention generally relates to a method of forming patterns of a semiconductor device and, more particularly, to a method of forming the patterns of a semiconductor device, which is capable of stabilizing a pattern formation process and securing process margin, although spacer patterning technology is used.
2. Brief Description of Related Technology
The patterns of a semiconductor device include cell patterns, which constitute the cell array of the semiconductor device, and test patterns formed under the same conditions (for example, material, thickness, width, and length) as the cell patterns to analyze the resistance of the cell patterns. The cell patterns are formed in a cell array region, and the test patterns are formed in a peripheral (peri) region that is narrower than the cell array region. The patterns of the semiconductor device become micro-sized with a high degree of integration of the semiconductor device.
Spacer patterning technology has been proposed as a method of forming the micro patterns of the semiconductor device. Spacer patterning technology includes a process of patterning an sacrificial pattern using a photoresist pattern as an etch barrier, a process of forming a spacer on the sidewalls of the sacrificial pattern, a process of removing the sacrificial pattern, a process of patterning a hard mask pattern using the spacer as an etch barrier, and a process of patterning the patterns of a semiconductor device using the hard mask pattern as an etch barrier. As described above, in spacer patterning technology, the shapes of the hard mask pattern and the cell patterns are defined by the spacer.
The above-described spacer is configured to surround the sidewalls of the sacrificial pattern having a specific width. More specifically, the spacer includes line spacers spaced apart from each other at a specific interval and interconnection spacers connecting both ends of the line spacers and formed at the sidewalls of both ends of the sacrificial pattern. Here, the interconnection spacers are removed before the hard mask pattern is formed. Accordingly, the shapes of the test patterns and the cell patterns are defined by the line spacers. On the other hand, pad units are formed at both ends of the test patterns and each has a width wider than that of the test patterns and functions as resistance measurement terminals. To this end, after the interconnection spacers are removed, a pad sacrificial pattern, having a width wider than the width of each of the line spacers, must be formed at both ends of the line spacer. In this case, since the interval between the line spacers formed in the peri region is narrow as in the cell array region, the pad sacrificial pattern does not overlap both ends of one line spacer, but connects two line spacers and overlaps therewith. The hard mask pattern is patterned using the pad sacrificial pattern and the line spacers having this form. The cell patterns, the test patterns, and the pad units are patterned using the hard mask pattern. Consequently, the test patterns have the same width and interval as the cell patterns. The pad units are configured to connect two test patterns and are formed at both ends of the test patterns. The resistance value of the cell pattern is analyzed through the test patterns and the pad units. To analyze the resistance value of the cell patterns, the resistance value of one of the test patterns formed under the same condition as the cell patterns must be known. However, since the pad units are formed to connect the two test patterns, the resistance value measured through the pad units to analyze the resistance value of the cell patterns must be divided in half.
On the other hand, to accurately analyze the resistance of the cell patterns, the test patterns must be formed under the same conditions as the cell patterns. If it is sought to form the test patterns under the same conditions as the cell patterns, the sizes of the photoresist patterns, functioning as the etch barriers, must be identical in the cell array region and the peri region when the sacrificial patterns are formed. In the case where the photoresist patterns having the same size are formed in the peri region and the cell array region, the densities of the photoresist patterns in the peri region and the cell array region must be uniform because of Depth of Focus (DOF) margin. Accordingly, dummy photoresist patterns are formed in the peri region. Through the dummy photoresist patterns, dummy sacrificial patterns are formed when the sacrificial patterns are formed, dummy spacers are formed when the spacers are formed, the dummy hard mask pattern is formed when the hard mask pattern is formed, and dummy patterns are formed when the cell patterns and the test patterns are formed. The dummy patterns are formed in a process of improving the stability of a process, but are not used to analyze the resistance of the cell patterns. Accordingly, the dummy patterns must be electrically isolated from the test patterns. However, if the width of the pad units formed at both ends of the test pattern is wider than the width of the test pattern, there is a danger that the dummy patterns might be connected to the pad units. To prevent this problem, the length of the dummy patterns is shorter than that of the test pattern. If it is sought to form the length of the dummy pattern shorter than that of the test pattern as described above, the length of the dummy sacrificial patterns must be shorter than that of other sacrificial patterns.
FIG. 1 is a diagram showing spacers formed by known methods.
Referring to FIG. 1, spacers include a first spacer 1 formed to define a test pattern, dummy spacers 3 formed for the stability of a process, and a second spacer 5 formed to define cell patterns. As described above, the first spacer 1 has the same shape as the second spacer 5, and the dummy spacers 3 are shorter than the first spacer 1. The spacers 1, 3, and 5 are divided into respective line spacers 1a, 3a, and 5a and respective interconnection spacers 1b, 3b, and 5b. Here, since regions where the test pattern, the dummy patterns, and the cell patterns will be formed are defined by the respective line spacers 1a, 3a, and 5a, the interconnection spacers 1b, 3b, and 5b must be removed.
The interconnection spacers 1b, 3b, and 5b are removed by an etch process using photoresist patterns PR as etch barriers. Regions where the photoresist patterns PR will be formed are defined depending on exposure mask alignment. In this case, since the dummy spacers 3 are shorter than the first spacer 1, the interconnection spacers 3b of the dummy spacers 3 and the interconnection spacer 1b of the first spacer 1 are not arranged on the same line. It makes it difficult to secure the alignment margin of an exposure mask in the test pattern region. Accordingly, the line spacer 1a of the first spacer 1 adjacent to the interconnection spacers 3b of the dummy spacers 3 is likely to be exposed as in a portion indicated by “X.” Consequently, failure is generated in the formation of the test pattern. Accordingly, there is a need for a method of stabilizing a pattern formation process and securing process margin, although spacer patterning technology is used.